1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a low-k (low dielectric constant) dielectric layer capable of reducing a signal delay time of a wiring by decreasing a dielectric constant of a dielectric layer used for manufacturing a semiconductor device such that the dielectric layer has a dielectric constant below 2.8.
2. Description of the Prior Art
In general, a silicon oxide layer is formed through a CVD (chemical vapor deposition) method or an SOG (spin on glass) method as an insulating layer for insulating a semiconductor device. When the silicon oxide layer is deposited, carbon and fluorine are added to the silicon oxide layer in order to decrease a dielectric constant of the silicon oxide layer.
However, when the dielectric constant of the silicon oxide layer is equal to or less than 2.8, there is a limitation to decrease the dielectric constant through the CVD method or the SOG method, so that a signal delay time of a wiring may increase.